Standard

JEDEC JEP147

Publisert
For bestilling og priser av dette produktet ta kontakt med salg@standard.no

Omfang

This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component. 

Dokumentinformasjon

  • Standard fra JEDEC_AC
  • Publisert:
  • Versjon: 0
  • Varetype: IS