Standard

JEDEC JEP147

Published

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Abstract

This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component. 

Document information

  • Standard from JEDEC_AC
  • Published:
  • Version: 0
  • Document type: IS