Standard

IEC 61691-5:2004 ED1

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Omfang

Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard

Dokumentinformasjon

  • Standard fra IEC
  • Publisert:
  • Tilbaketrukket:
  • Utgave: 1
  • Versjon: 1
  • Varetype: IS
  • ICS 25.040.01
  • ICS 35.060
  • ISO TC TC 91

Produktrelasjon