Standard

IEC 61691-5:2004 ED1

Oct 2004 Withdrawn

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Language English

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Abstract

Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard

Document information

Standard from IEC
Published: 7 October 2004
Withdrawn: 3 August 2010
Edition: 1
Version: 1
Document type: IS
ISBN: 2831876842

ICS 25.040.01
ICS 35.060
ISO TC TC 91

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Adopted by: NEK IEC 60169-8:1978

IEC 61691-5:2004 ED1

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Abstract

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Abstract

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