Standard

IEC 62530:2007 ED1

Nov 2007 Revised

Note: This standard has a new edition: IEC 62530:2021 ED3

Corrigendums and amendments are bought separately.

Language English

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Abstract

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

Document information

Standard from IEC
Published: 7 November 2007
Withdrawn: 19 May 2011
Edition: 1
Version: 1
Document type: IS
Pages
ISBN: 2831893496

ICS 25.040.01
ISO TC TC 91

Product Relations

Revised by: IEC 62530:2011 ED2

IEC 62530:2007 ED1

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IEC 62530:2021 ED3

IEC 62530:2011 ED2