Standard

IEC 62142:2005 ED1

Jun 2005 Withdrawn

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Abstract

Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

Document information

Standard from IEC
Published: 27 June 2005
Withdrawn: 4 August 2010
Edition: 1
Version: 1
Document type: IS
ISBN: 283188036X

ICS 25.040.99
ISO TC TC 91

IEC 62142:2005 ED1

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Abstract

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Access to standards for the entire organization

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Abstract

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