Standard

NEK IEC 62142:2005

Jun 2005 Withdrawn

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Language English

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Abstract

Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

Document information

Standard from NEK
Published: 27 June 2005
Withdrawn: 4 August 2010
Edition: 1.0
Version: 1
Document type: NAT
ISBN:

ICS 25.040.99
National Committee TC 91

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Adopted from: IEC 60598-2-20:2014 ED4
Adopted from: IEC 62142:2005

NEK IEC 62142:2005

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Abstract

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Abstract

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