Standard

NEK IEC 61523-2:2002

May 2002 Withdrawn

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Abstract

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

Document information

Standard from NEK
Published: 17 May 2002
Withdrawn: 1 June 2011
Edition: 1.0
Version: 1
Document type: NAT
ISBN:

ICS 35.240.50
National Committee NEK/NK91

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Adopted from: IEC 62395-2:2013 ED1
Adopted from: IEC 61523-2:2002

NEK IEC 61523-2:2002

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Abstract

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Abstract

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