Standard

JEDEC JESD323B

Published

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Abstract

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs), and 288-pin, 1.1 V (VDD), Clocked, Quad rank unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CQDIMMs). These DDR5 SDRAM CUDIMMs and DDR5 SDRAM CQDIMMs are intended for use as main memory when installed in computers. The CQDIMM has additional chip select signals at the connector pins where they were RFUs for the CUDIMM. Reference design examples are included which provide an initial basis for DDR5 CUDIMM and CQDIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity, and thermal requirements for PC5-6400 and up to PC5-9200 support. All DDR5 CUDIMM and CQDIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. Reference design specific design specification/design rule which deviated from this common standard are documented in the Design Deviation section of each reference design’s annex.

Document information

  • Standard from JEDEC_AC
  • Published:
  • Version: 0
  • Document type: IS
  • Additional information
    • Version 2.0