Standard

JEDEC JEP375

Published

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Abstract

Key process elements of 2.5D/3D chip stacking technologies are Copper Through Silicon Vias (Cu-TSVs) with wafer thinning followed by a Backside Redistribution Layer (RDL) process. The intent of this publication is to provide guidelines for a minimal reliability characterization of 2.5D/3D processed thinned wafers with Cu-TSVs and Backside RDL. These guidelines only apply to Cu-TSVs and do not apply to any other TSV metallization. These guidelines include the characterization of thinned wafers with the TSV via first, middle, or last process.  The reader is referred to JEP158 for guidelines on Multiple Bonded Wafers characterization.  This publication is limited to the introduction of the 2.5D/3D process elements applied to a fully qualified 2D CMOS technology. This includes standard planar MOSFET, FinFET and future CMOS technologies. In addition, the scope is limited to TSV introduction in Silicon Bulk Technologies.  The 2.5D/3D reliability characterization is focused on quantifying:  • The delta between the 2D thick and the 2.5D/3D thinned wafers with respect to the 2D CMOS FEOL/MOL/BEOL intrinsic wear mechanisms.  • The intrinsic reliability wear-out mechanisms associated with the introduction of TSVs, the Backside RDL and wafer thinning.  This thinned wafer is associated with either 3D (a) or 2.5D (b) packaging. This DUT is part of a 2.5D/3D double flipped process (c) described further. This double flipped process allows the DUT to be tested using BEOL pads as was done for 2D thick wafers. It is expected that the double flipped process will not impact the reliability of the 2.5D/3D thinned wafer delivered to the customer. Most of the recommended reliability evaluation is based on Wafer Level Reliability (WLR) testing, but, when needed, the use of module (proxy package) level stressing is recommended as part of the 2.5D/3D reliability evaluation. These tests are performed on a combination of 2D thick wafers, 2.5D/3D thick wafers, and 2.5D/3D thinned wafers depending on the reliability mechanism to be evaluated. The selected wafers for this testing are 2D wafers and 2.5D/3D wafers manufactured with the process of record adopted for 2.5D/3D product. In addition, guidelines on recommended structures to be used for the 2.5D/3D WLR evaluation are provided. This publication assumes:  1) 2D Technology Qualification.  a. It is assumed that it has been completed prior to the addition of 2.5D/3D elements and that it is manufacturable.  2) 2.5D/3D Elements introduced into the 2D technology covered in this publication.  a. Copper Through Silicon Vias  b. Wafer Thinning  c. Backside Redistribution Layer Process  This publication covers the minimum guidelines on the following 2.5D/3D reliability qualification items:  1) Requalification of the 2D FEOL/MOL/BEOL reliability elements (Intrinsic wear out mechanisms, defect density) with the added 2.5D/3D elements.  a. Using the same stress and test methodology originally done on the already qualified 2D CMOS processes.  2) Additional reliability testing needed on the 2D CMOS elements due to added 2.5D/3D Elements.  a. Clause 5.  i. TSV Mechanical Proximity Effects.  ii. Global Effects (2.5D/3D effects to 2.0D CMOS technology in addition to mechanical proximity effects).  iii. Plasma Induced Damage (Possible PID damage to 2D FEOL due to introduction of the 2.5D/3D elements into the 2D CMOS process).  b. Clause 8 – Impact of Stress Migration and Thermal Cycling to 2D BEOL reliability due to the introduction of the 2.5D/3D elements.  c. Clause 9 – Impact of SM/HTS and Thermal Cycling to the 2D FEOL/MOL reliability due to the 2.5D/3D elements.  3) 2.5D/3D key reliability Qualifications elements.  a. Clause 6 – Cu-TSV Electromigration (EM).  b. Clause 7 – Cu-TSV (Dielectric/Metallic Liner), TSV/RDL and TSV/Mx interface integrity.  c. Clause 9 – Impact of SM/HTS and TC on Cu TSV, TSV/RDL & TSV/Mx interface integrity.  This publication does not cover any additional processing after wafer thinning (bumps, 2.5D/3D packaging, etc.) and is not meant to be a comprehensive document, as additional tests may be required based upon specific process/packaging requirements not covered here. Full qualification should come from an agreement between the customer and the supplier.

Document information

  • Standard from JEDEC_AC
  • Published:
  • Version: 0
  • Document type: IS