Standard

JEDEC JEP202

Published

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Abstract

Threshold voltage VT is the one of most important parameters of MOS device. VT knowledge is vital for system designers, since it defines switching behavior of the device. Typically, in the datasheets it is defined as the gate voltage at which the drain current crosses certain threshold value. Often VT is also measured under conditions that do not occur in real-world applications. In some cases, a fixed low VDS is used as the test condition, but usually measured with gate and drain shorted together. Such definition of threshold voltage has not much use for system designers. In addition, and with focus on SiC-based MOS devices, threshold voltage depends strongly on measurement setup and pre-conditions as well which needs be considered during evaluating and comparing switching behavior of devices.  This document focuses on the features of silicon carbide MOS gated devices and their implications on device threshold voltage. To maximize the quality and especially practical worth of the data sheet data, the guidance for threshold voltage representation in such documents is provided.

Document information

  • Standard from JEDEC_AC
  • Published:
  • Version: 0
  • Document type: IS
  • Additional information
    • Version 1.0